An Interactive System Level Simulation Environment for Systems- on-Chip

International audienceThis article presents an interactive simulation environment for high level models intended for Design Space Exploration of Systems-On-Chip. The existing open source development environment TTool supports the MARTE compliant UML profile DIPLODOCUS and enables the designer to create, simulate and formally verify models. The goal is to obtain first performance estimations of the system intended for design while minimizing the modeling effort. The contribution outlined in this paper is an additional module providing means for controlling the simulation in real time by performing step wise execution, saving and restoring simulation states as well as animating UML models of the system. Moreover the paper elaborates on the integration of these new features into the existing framework consisting of a simulation engine on the one hand and a graphical user interface on the other hand

Un environnement de conception de systèmes distribués basé sur UML

Cet article propose un nouvel environnement de développement des systèmes distribués, basé sur le profil UML TURTLE. Aux étapes d'analyse et de conception qui firent l'objet de précédents articles, nous ajoutons une étape de déploiement. Il s'agit en l'occurrence de déployer des composants TURTLE sur des noeuds matériels d'exécution et de modéliser les liens entre ces noeuds d'exécution. A l'exemple des diagrammes TURTLE utilisés en analyse et conception, les diagrammes de déploiement se voient dotés d'une sémantique formelle par traduction vers le langage RT-LOTOS. L'outil TTool (TURTLE Toolkit) est enrichi d'un générateur de code exécutable Java capable de prendre en compte les composants TURTLE déployés sur des noeuds et les liens entre les noeuds d'exécution. TTool génère maintenant du code réseau qui utilise les protocoles de type UDP ou RMI pour assurer les communications entre composants. L'intrusion d'un pirate dans une session HTTP sécurisée sert d'exemple illustratif de l'environnement proposé

Architectures for Cognitive Radio Testbeds and Demonstrators – An Overview

Wireless communication standards are developed at an ever-increasing rate of pace, and significant amounts of effort is put into research for new communication methods and concepts. On the physical layer, such topics include MIMO, cooperative communication, and error control coding, whereas research on the medium access layer includes link control, network topology, and cognitive radio. At the same time, implementations are moving from traditional fixed hardware architectures towards software, allowing more efficient development. Today, field-programmable gate arrays (FPGAs) and regular desktop computers are fast enough to handle complete baseband processing chains, and there are several platforms, both open-source and commercial, providing such solutions. The aims of this paper is to give an overview of five of the available platforms and their characteristics, and compare the features and performance measures of the different systems

Confidentialité et intégrité du bus mémoire

La sécurité de l'exécution du programme est souvent demandée pour les applications critiques. Malheureusement elle est vulnérable à beaucoup de techniques d'attaques telles que les exploitations logicielles et les attaques du matériel. Certaines des expériences existantes ont déjà démontré que la sécurite de la communication entre le processeur et la mémoire externe peut être compromise par les attaques par sondage sur carte. Généralement les attaques par sondage sont divisées en deux sous-classes : le sondage passif et le sondage actif. Dans le premier cas, un attaquant peut capturer des données critiques pendant le processus de communication entre le processeur et la mémoire. le sondage actif peut être utilisé pour altérer les données de la mémoire afin de compromettre l'exécution du programme dans le processeur. Le premier cas se réfère a la confidentialité des données de la mémoire et le second a l'intégrite des données de la mémoire. cette thèse vise à explorer les options diverses pour protéger la confidentialité et l'intégrite du bus mémoire contre ces attaques par sondage sur carte. L idée fondamentale de la protection converge sur l'implémentation d'un moteur cryptographique matériel interne au circuit afin de garantir l'intégrite et la confidentialité des données venant de la mémoire. Comme notre marche visé est celui des systémes embarqués faibles-à-moyens, nous nous efforcons de proposer un schéma de protection réaliste, acceptable par le marché, avec des coûts faibles. Toutes ces contraintes fortes influencent largement nos choix spécifiques pour la protection.The security of program execution is often required for certain critical applications. Unfortunately she is vulnerable to many attacking techniques such as software exploits and hardware attacks. Some existing experiences denote that the security of communication between processor and memory can be compromised by board-level probing attacks. Generally probing attacks are divided into two sub-classes : passive probing and active probing. in the first case, an attacker can capture critical data during the process of processor-memory communication. The active probing attacks can be used to alter memory data in order to compromise the program execution in the processor. The first case is related to the confidentiality of memory data and the latter to the integrity of memory data. This dissertation aims to explore diverse options to protect the confidentiality and integrity of memory bus against board-level probing attacks. The fundamental idea focuses on the implementation of an on-chip hardware cryptographique engine to guarantee the integrity and confidentiality of memory data. As our target market is low-to-medium embedded systems, we intend to propose one protection scheme which is realistic, acceptable-to-market and with low costs. all such strong constraints leverage bigly our specific protection choice.PARIS-Télécom ParisTech (751132302) / SudocSudocFranceF

Deployment Path For a 'Route Automatisée' Project in a French Metropolitan Transportation Context

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Differential Power Analysis Model and Some Results

Abstract CMOS gates consume different amounts of power whether their output has a falling or a rising edge. Therefore the overall power consumption of a CMOS circuit leaks information about the activity of every single gate. This explains why, using differential power analysis (DPA), one can infer the value of specific nodes within a chip by monitoring its global power consumption only. We model the information leakage in the framework used by conventional cryptanalysis. The information an attacker can gain is derived as the autocorrelation of the Hamming weight of the guessed value for the key. This model is validated by an exhaustive electrical simulation. Our model proves that the DPA signal-to-noise ratio increases when the resistance of the substitution box against linear cryptanalysis increases. This result shows that the better shielded against linear cryptanalysis a block cipher is, the more vulnerable it is to side-channel attacks such as DPA

A Model-Driven Engineering Methodology to Design Parallel and Distributed Embedded Systems

International audience<p>In MDE system-level approaches, the design of communication protocols and patterns is subject to the design of processing operations (computations) and to their mapping onto execution resources. However, this strategy allows to capture simple communication schemes (e.g., processor-bus-memory) and prevents to evaluate the performance of both computations and communications (e.g., impact of application traffic patterns onto the communication interconnect) in a single step. To solve these issues we introduce a novel design approach - the Ψ-chart - where we design communication patterns and protocols independently of a system’s functionality and resources, via dedicated models. At the mapping step, both application and communication models are bound to the platform resources and transformed to explore design alternatives for both computations and communications. We present the Ψ-chart and its implementation (i.e., communication models and Design Space Exploration) in TTool/DIPLODOCUS, a UML/SysML framework for the modeling, simulation, formal verification and automatic code generation of data-flow embedded systems. The effectiveness of our solution in terms of better design quality (e.g., portability, time) is demonstrated with the design of the physical layer of a ZigBee (IEEE 802.15.4) transmitter onto a multi-processor architecture.</p

Dynamic guest memory resizing for disaggregated systems – paravirtualized approach

International audienc

DiplodocusDF: Analyzing Hardware/Software Interactions with a Dinosaur

<p>Development of new products commonly relies on existing designs where hardwareand software are modeled separately and their interactions investigated late atverification time. Composing hardware with software yields more than thesum of the two parts and solid design dedicates a great deal of time and moneyto understand their interactions. This paper presents a novel modelingmethodology based on DiplodocusDF, a UML Model-Driven Engineering approachfor the design of heterogeneous data processing systems.Our methodology separately models conflicting aspects such as communicationsversus computations, dataflow versus controlflow and allows for their impact onthe overall system's performance to be separately analyzed at variousabstraction levels. Our methodology is applied to a case study which shows howit is possible to study interactions parallel to design, thusgreatly reducing time-to-market of new products and comprehension of existing designs.</p